Research

Architecting Efficient and Reliable AI Systems

The progress of artificial intelligence is increasingly limited not only by what models can learn and how accurately they can perform, but also by how efficiently and reliably computing systems execute those models. Accuracy alone is insufficient if a model is too costly to deploy, misses a real-time deadline, or produces untrustworthy results because of a system fault. I highlight two trends that make efficiency and reliability central challenges for AI systems: scaling up and scaling out.

Scaling up

In the era of large language models (LLMs), training and inference span large fleets of accelerators, memory systems, and networked infrastructure. At this scale, modest inefficiencies multiply into substantial energy and infrastructure costs. Meanwhile, rare hardware faults can be amplified across a fleet and become recurring service disruptions. Scaling model capabilities therefore requires architectures that improve efficiency while sustaining reliability across heterogeneous platforms.

Scaling out

AI is also moving beyond data centers into edge and embedded devices, embodied agents, scientific instruments, and the Internet of Things (IoT). These platforms must execute AI under tight energy, memory, and latency budgets, often in changing or safety-sensitive environments. Here, efficiency determines whether intelligence can be deployed at all, and reliability determines whether it can be trusted.

How should we architect AI systems when efficiency and reliability are primary design objectives?

My central approach is cross-layer co-design: architecture must account for model structure, workload behavior, and application requirements, while models and runtimes must expose where computation can be reduced, adapted, or protected. I pursue this vision through three mutually reinforcing fronts.

1 Hardware/software co-design for efficient and reliable ML systems Connecting hardware faults, model behavior, and runtime protection.
2 Emerging computing schemes such as approximate and bio-inspired computing Promising alternatives to conventional deep learning.
3 Computer architecture for AI/ML-enabled brain–computer interfaces Continuous, low-latency, and trustworthy neural processing.

1Hardware/Software Co-design for Efficient and Reliable Machine Learning Systems

At scale, failures such as hardware errors and silent data corruptions become inevitable. ML workloads, however, exhibit distinct fault characteristics and reliability demands. A fault's effect depends on where it occurs, the workload being processed, and how it propagates through the system. My work replaces uniform protection with workload-aware reliability: understanding faults at the hardware level, characterizing their application-level consequences, and applying application-tailored techniques to provide more effective, fine-grained protection.

Characterizing silent data corruption

I developed PyTEI, a fast and flexible error-injection framework for studying silent data corruption (SDC) in large ML models, and subsequently open-sourced it through Meta's research platform [ISSRE'25]. Its parallel design makes broad campaigns practical and reveals vulnerability patterns that aggregate hardware metrics miss. In deep recommender systems, for example, I found that multilayer perceptrons are substantially more vulnerable than embedding tables, motivating component-specific mitigation techniques. I have extended this empirical approach to transformer models, examining how architecture and workload influence the propagation of hardware errors [ACNS'26].

Cross-layer detection and mitigation

I also designed Dr. DNA, which detects SDC through distributional signatures in intermediate neural activations and mitigates errors during inference [ASPLOS'24]. Because it observes semantic behavior inside the model, Dr. DNA can detect and mitigate stealthy or delayed manifestations that are difficult to recognize from hardware symptoms alone, while incurring low overhead. My context-aware modeling further showed that hardware error behavior varies with workload inputs and operating conditions [TCAD'20, TCAD'21].

2Emerging Computing Schemes such as Approximate Computing and Bio-inspired Computing

Emerging computing schemes seek novel solutions that complement mainstream computing paradigms. My research on this front focuses on two such schemes: approximate computing, which exploits tolerance within an ML workload to trade accuracy for efficiency gains, and hyperdimensional computing (HDC), which offers a bio-inspired representation and learning paradigm. In both cases, my goal is to make efficiency gains controllable and the resulting behavior reliable.

Approximation guided by workload semantics

I developed methods that place approximation according to the nonuniform sensitivity of a model. AxR-NN assigns layer-specific computation-reuse settings through design-space exploration, reducing work while respecting an accuracy target [GLSVLSI'20]. AxBy identifies and bypasses low-value computations, avoiding work rather than merely executing it at lower precision [Euromicro DSD'20]. I later applied the same principle at the data-representation level: approximate rotary compositional embeddings reduce the memory footprint of deep recommender systems [SIGIR'24].

Bio-inspired hyperdimensional computing

HDC represents information with high-dimensional vectors and learns through simple, highly parallel operations, making it attractive for memory- and energy-constrained systems [CODES+ISSS'22]. I pioneered HDC applications in several domains, including memory-efficient spam detection, molecular-property prediction, and fast performance ranking for neural architecture search [ISVLSI'21, BIBM'22, CVPRW-NAS'23]. I also led systematic studies of HDC's adversarial behavior across white-box, gray-box, and black-box threat models and developed specialized testing and defense methods [DAC'21, TCAD'23]. My recent work continues this systems view through multilayer reliability evaluation of HDC implementations [IJCNN'26].

3Computer Architecture for AI/ML Enabled Brain–Computer Interfaces

Brain–computer interfaces (BCIs) translate neural activity into information for communication, rehabilitation, or control. Real-time, closed-loop BCIs must interpret continuous, noisy, and patient-specific signals under tight latency, energy, privacy, and reliability constraints. Researchers have also begun incorporating AI into BCI pipelines to leverage the ability of learning methods to decode and classify complex neural signals. These demands make BCI a compelling testbed for efficient and reliable computer architectures and systems for AI.

From offline accuracy to online interfaces

I developed deep-learning methods to classify walking tasks in older adults, showing how ML can extract useful representations from physiological time series [TNSRE'23]. I also contributed to real-time spike sorting, which associates neural-probe events with individual neurons for downstream tasks [NER'25]. Through this work, I identified a common gap: BCI algorithms increasingly use AI but are often evaluated without considering efficiency and reliability. In particular, strong "offline" accuracy does not automatically produce an effective "online" interface.

Architecting the BCI pipeline

I am currently working to architect the complete BCI pipeline as a unified computing system that jointly considers reliability and efficiency. Specifically, I am developing BCI serving backends that accelerate state-of-the-art spike sorting by up to 2× while guaranteeing run-to-run determinism as a foundation for reliable execution. In this research program, BCI serves both as a high-impact application and as a driver for broadly useful architectures for real-time scientific AI.

Future directions

Efficiency and reliability by design across the AI stack

Today's AI systems commonly treat efficiency and reliability as afterthoughts: a model is first optimized for accuracy, then compressed, accelerated, or protected after deployment problems appear. I envision an AI stack in which these objectives shape the design from the beginning. At the model level, I will enable efficiency- and reliability-aware training and architecture search. At the systems level, I will develop compilers and runtimes that choose kernels, data formats, mappings, and recovery policies according to workload and service objectives. At the architecture level, I will design compute primitives that expose adaptable precision, redundancy, and monitoring mechanisms. Connecting these layers can enable AI infrastructure that continuously optimizes useful work per joule while maintaining explicit guarantees on output quality and availability.
Efficient and dependable systems for agentic AI

Agentic AI systems introduce a new kind of scale through their enormous compute demands. Their workloads are also dynamic, difficult to predict in advance, and often interact with mission-critical systems or the physical world through embodied agents. I will explore architectures and systems that execute agentic AI efficiently and reliably. The goal is to make agents not only more capable, but also resource-bounded and dependable enough for sustained operation.
Architecture as an enabler for AI for Science

My research in BCI is an ideal starting point for a broader effort in AI for Science because many scientific domains face similar efficiency and reliability demands. I will generalize the streaming, adaptive, and reliability-aware principles developed for BCI into architectures and software abstractions for scientific discovery. By co-designing computing systems with scientists and domain experts, this direction can make advanced AI more accessible to the broader scientific community.

My long-term research goal is to establish efficiency and reliability as foundational principles for intelligent computing. By connecting AI models to the architectures, systems, and scientific contexts in which they operate, I aim to enable intelligence that scales up and scales out without sacrificing efficiency or reliability for capability.